In recent years, there has been increasing demand in the field of business applications for improvement of response speed and the like. Business applications include applications for securities trading, database processing, game playing, and the like. In securities trading systems, for example, the acceptable range of time until consummation of a transaction was conventionally measured by the millisecond, but in recent years, has been measured by microsecond. In addition, database processing has needed higher IOPS (input/output per second). Further, in recent game playing, real-time performance has been of increasing importance, and higher-speed processing has been requested.
Because of this situation, in the field of business applications, low-delay inter-server communication techniques have been increasingly used to shorten the time of communications between servers.
As a low-delay inter-server communication technique, for example, there has been provided InfiniBand allowing communication of 1 μsec or less in one way in the field of high performance computing (HPC) with super computers.
In such a low-delay inter-server communication technique, an interruption system or polling system may be used as a reception detecting system for detection of data reception.
In the interruption system, an interrupt is generated upon receipt of data, and a data receiving process is executed with the generation of the interrupt as an impetus. Meanwhile, in the polling system, while the data receiving process is started, polling is performed to check if any data is received on a periodic basis, and when the data is received, the receiving process proceeds. In the interruption system, since the receiving process is started after generation of an interrupt, the delay may be 2 to 3 μsec. Meanwhile, in the polling system, the receiving process is started from the beginning, which makes it possible to keep the delay as shorter as 1 μsec or less than in the interruption system. However, in the polling system, a component performing process is occupied during execution of polling. For example, when processes are assigned to each of CPU (central processing unit) cores as computing units in the polling system, one CPU core is occupied by the data receiving process.
In this regard, in the case of using conventional HPC applications, the number of processes executed falls under the number of CPU cores, and thus occupation of CPU cores by the data receiving process has few harmful effects even when the detection of reception is performed in the polling system. In the case of using the case of business applications, however, the number of processes executed is large and exceeds the number of CPU cores. In this case, the occupation of CPU cores by the data receiving process may have influence on other processes.
To avoid the occupation of CPU cores, there has been suggested polling technique using SMT (simultaneous multi-threading). The SMT refers to a CPU function by which a program is divided into threads to be individually processed by CPU cores or execution units included in the CPU cores as computing units, and the threads are processed simultaneously by the plurality of CPU cores or execution units. When polling is performed using SMT, for example, the CPU cores or the execution units are operated such that one thread is used for execution of an application and another for execution of polling. The thread for polling will be hereinafter called “communication control thread.” Thus, the data receiving process with polling occupies only the communication control thread, and the CPU cores or the execution units can execute applications using another thread even during execution of the polling.
There is a conventional multi-tasking technique for a plurality of CPU cores to execute different processes, by which each of the CPU cores request execution of processes from peripheral devices, and tasks of CPU cores waiting for processing results are given lower priority. In addition, there is a conventional technique by which, after a request for execution of a process is issued to an I/O driver, when a load on an operation system (OS) is equal to or less than a predetermined value, a request for an interrupt is disabled and polling is conducted on the I/O device, and then after lapse of a predetermined period of time, a request for an interrupt is enabled.
Further, there is a conventional technique by which an auxiliary processing device is provided to execute tasks instead of a main processing device, and the main processing device is shifted to a power-saving mode according to operations of the auxiliary processing device.    Patent Literature 1: Japanese Laid-open Patent Publication No. 2006-260377    Patent Literature 2: Japanese Laid-open Patent Publication No. 2001-216170    Patent Literature 3: Japanese Laid-open Patent Publication No. 2005-346708
However, even in the case of using SMT, CPU core resources are used in common by the threads. Accordingly, consumption of the CPU core resources during polling with a communication control thread may lead to deterioration in performance of the thread for executing applications.
The technique for an auxiliary processing device to execute tasks is intended to control operations in the power-saving mode corresponding to the polling status, and does not take into account the influence of polling on execution of applications. It is thus difficult to reduce influence of polling on processing of applications even with the use of this technique. In addition, the conventional technique for a plurality of CPU cores to make individual requests for processing from peripheral devices and the conventional technique for polling when a load on OS is equal to or less than a predetermined value, are targeted at multi-tasking in which each CPU core performs a process, and do not take into account the case of using SMT. Therefore, even with the use of the foregoing conventional techniques, it is difficult to achieve a balance between high communication performance and high application processing capability in the situation where a plurality of threads is operated in one CPU core such as SMT.